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FEATURES

LT3845 High Voltage Synchronous Current Mode Step-Down Controller with Adjustable Operating Frequency DESCRIPTION
The LT(R)3845 is a high voltage, synchronous, current mode controller used for medium to high power, high efficiency supplies. It offers a wide 4V to 60V input range (7.5V minimum start-up voltage). An onboard regulator simplifies the biasing requirements by providing IC power directly from VIN. Burst Mode(R) operation maintains high efficiency at light loads by reducing IC quiescent current to 120A. Light load efficiency is also improved with the reverse inductor current inhibit function which supports discontinuous operation. Additional features include adjustable fixed operating frequency that can be synchronized to an external clock for noise sensitive applications, gate drivers capable of driving large N-channel MOSFETs, a precision undervoltage lockout, 10A shutdown current, short-circuit protection and a programmable soft-start. The LT3845 is available in a 16-lead thermally enhanced TSSOP package.
, LT LTC and LTM are registered trademarks of Linear Technology Corporation. , Burst Mode is a registered trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 6611131, 6304066, 6498466, 6580258.

High Voltage Operation: Up to 60V Synchronizable Up to 600kHz Adjustable Constant Frequency: 100kHz to 500kHz Output Voltages Up to 36V Adaptive Nonoverlap Circuitry Prevents Switch Shoot-Through Reverse Inductor Current Inhibit for Discontinuous Operation Improves Efficiency with Light Loads Programmable Soft-Start 120A No Load Quiescent Current 10A Shutdown Supply Current 1% Regulation Accuracy Standard Gate N-Channel Power MOSFETs Current Limit Unaffected by Duty Cycle Reverse Overcurrent Protection 16-Lead Thermally Enhanced TSSOP Package
APPLICATIONS

12V and 42V Automotive and Heavy Equipment 48V Telecom Power Supplies Avionics and Industrial Control Systems Distributed Power Converters
TYPICAL APPLICATION
High Voltage Step-Down Regulator 48V to 12V at 75W
VIN 20V TO 55V 100 2.2F 100V 47F 63V 82.5k 1500pF 0.1F 1M VIN SHDN CSS LT3845 BOOST TG SW VCC BG PGND SENSE
+
Efficiency and Power Loss vs Load Current
VIN = 48V 7 6 5 4 3 2 LOSS 70 1 0 1 LOAD CURENT (A) 10
3845 TA01b
95 Si7370DP 0.01 BAS521 Si7370DP 15H B160 EFFICIENCY(%) VOUT 12V 75W 33F x3 90 85 80 75
POWER LOSS (W)
BURST_EN 20k 16.2k 2200pF 143k 49.9k 100pF SYNC fSET SGND VFB VC
SENSE-
1F 1N4148
3845 TA01a
65 0.1
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LT3845 ABSOLUTE MAXIMUM RATINGS
(Note 1)
PIN CONFIGURATION
TOP VIEW VIN SHDN CSS BURST_EN VFB VC SYNC fSET 1 2 3 4 5 6 7 8 17 16 BOOST 15 TG 14 SW 13 VCC 12 BG 11 PGND 10 SENSE+ 9 SENSE-
Input Supply Voltage (VIN) ........................................65V Boosted Supply Voltage (BOOST) .............................80V Switch Voltage (SW) (Note 8) ....................... 65V to -2V Differential Boost Voltage (BOOST to SW).....................................................24V Bias Supply Voltage (VCC) .........................................24V SENSE+ and SENSE- Voltages ..................................40V Differential Sense Voltage (SENSE+ to SENSE-)................................... 1V to -1V BURST_EN Voltage ...................................................24V SYNC, VC, VFB, CSS, and SHDN Voltages ....................5V SHDN Pin Currents ..................................................1mA Operating Junction Temperature Range (Note 2) LT3845E (Note 3) ............................... -40C to 125C LT3845I .............................................. -40C to 125C Storage Temperature.............................. -65C to 150C Lead Temperature (Soldering, 10 sec) .................. 300C
FE PACKAGE 16-LEAD PLASTIC TSSOP TJMAX = 125C, JA = 40C/W, JC = 10C/W EXPOSED PAD (PIN 17) IS SGND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH LT3845EFE#PBF LT3845IFE#PBF TAPE AND REEL LT3845EFE#TRPBF LT3845IFE#TRPBF PART MARKING 3845FE 3845FE PACKAGE DESCRIPTION 16-Lead Plastic TSSOP 16-Lead Plastic TSSOP TEMPERATURE RANGE -40C to 125C -40C to 125C
Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LT3845 ELECTRICAL CHARACTERISTICS
PARAMETER VIN Operating Voltage Range (Note 4) VIN Minimum Start Voltage VIN UVLO Threshold (Falling) VIN UVLO Threshold Hysteresis VIN Supply Current VIN Burst Mode Current VIN Shutdown Current BOOST Operating Voltage Range BOOST Operating Voltage Range (Note 5) BOOST UVLO Threshold (Rising) BOOST UVLO Threshold Hysteresis BOOST Supply Current (Note 6) BOOST Burst Mode Current BOOST Shutdown Current VCC Operating Voltage Range (Note 5) VCC Output Voltage VCC UVLO Threshold (Rising) VCC UVLO Threshold Hysteresis VCC Supply Current (Note 6) VCC Burst Mode Current VCC Shutdown Current VCC Current Limit Error Amp Reference Voltage VFB Pin Input Current SHDN Enable Threshold (Rising) SHDN Threshold Hysteresis Sense Pins Common Mode Range Current Limit Sense Voltage Reverse Protect Sense Voltage Reverse Current Inhibit Offset Input Current (ISENSE+ + ISENSE-) VSENSE+ - VSENSE- VSENSE+ - VSENSE-, VBURST_EN = VCC VBURST_EN = 0V or VBURST_EN = VFB VSENSE(CM) = 0V VSENSE(CM) = 2V VSENSE(CM) > 4V
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 20V, VCC = BOOST = BURST_EN = 10V, SHDN = 2V, RSET = 49.9k, SENSE - = SENSE+ = 10V, SGND = PGND = SW = SYNC = 0V, unless otherwise noted.
CONDITIONS

MIN 4 3.6
TYP
MAX 60 7.5 4
UNITS V V V mV A A A V V V mV mA A A
3.8 670 20 20 9
VCC > 9V VBURST_EN = 0V, VFB = 1.35V VSHDN = 0V VBOOST - VSW VBOOST - VSW VBOOST - VSW VBURST_EN = 0V VSHDN = 0V Over Full Line and Load Range

15 75 20
5 400 1.4 0.1 0.1

8 6.25 500 3 100 20 -150 1.231 25
20 8.3
V V V mV mA A A mA V V nA V mV V mV mV mV A A A
3.7
VBURST_EN = 0V VSHDN = 0V Measured at VFB Pin VFB = 1.231V

-40 1.224 1.215 1.3 0 90
1.238 1.245 1.4 36 115

1.35 120 100 -100 10 800 -20 -300
Operating Frequency Minimum Programmable Frequency Maximum Programmable Frequency External Sync Frequency Range SYNC Input Resistance SYNC Voltage Threshold Soft-Start Capacitor Control Current Error Amp Transconductance Error Amp DC Voltage Gain Error Amp Sink/Source Current

290 270 500 100
300
310 330 100 600
kHz kHz kHz kHz kHz k V A S dB A
40 1.4 2 270 340 62 30 410 2
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LT3845 ELECTRICAL CHARACTERISTICS
PARAMETER TG, BG Drive On Voltage (Note 7) TG, BG Drive Off Voltage TG, BG Drive Rise/Fall Time Minimum TG Off Time Minimum TG On Time Gate Drive Nonoverlap Time TG Fall to BG Rise BG Fall to TG Rise
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 20V, VCC = BOOST = BURST_EN = 10V, SHDN = 2V, RSET = 49.9k, SENSE - = SENSE+ = 10V, SGND = PGND = SW = SYNC = 0V, unless otherwise noted.
CONDITIONS CLOAD = 3300pF CLOAD = 3300pF 10% to 90% or 90% to 10%, CLOAD = 3300pF

MIN
TYP 9.8 0.1 50 350 250 200 150
MAX
UNITS V V ns
650 400
ns ns ns ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3845 includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 3: The LT3845E is guaranteed to meet performance specifications from 0C to 125C junction temperature. Specifications over the - 40C to 125C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3845I is guaranteed over the full -40C to 125C operating junction temperature range.
Note 4: VIN voltages below the start-up threshold (7.5V) are only supported when the VCC is externally driven above 6.5V. Note 5: Operating range is dictated by MOSFET absolute maximum VGS. Note 6: Supply current specification does not include switch drive currents. Actual supply currents will be higher. Note 7: DC measurement of gate drive output "ON" voltage is typically 8.6V. Internal dynamic bootstrap operation yields typical gate "ON" voltages of 9.8V during standard switching operation. Standard operation gate "ON" voltage is not tested but guaranteed by design. Note 8: The -2V absolute maximum on the SW pin is a transient condition. It is guaranteed by design and not subject to test.
TYPICAL PERFORMANCE CHARACTERISTICS
Shutdown Threshold (Rising) vs Temperature
1.38 SHUTDOWN THRESHOLD, FALLING (V) SHUTDOWN THRESHOLD, RISING (V) 1.37 1.36 1.35 1.34 1.33 1.32 -50 -25 1.26 1.25 1.24 1.23 1.22 1.21 1.20 -50 -25 VCC (V)
Shutdown Threshold (Falling) vs Temperature
8.2 8.1 8.0 7.9 7.8 7.7 7.6
VCC vs Temperature
ICC = 20mA
0 25 50 75 TEMPERATURE (C)
100
125
0 25 50 75 TEMPERATURE (C)
100
125
7.5 -50 -25
0 25 50 75 TEMPERATURE (C)
100
125
3845 G01
3845 G02
3845 G03
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LT3845 TYPICAL PERFORMANCE CHARACTERISTICS
VCC vs ICC(LOAD)
8.05 TA = 25C 9 8 8.00 7 VCC (V) 7.95 VCC (V) 6 5 7.90 4 7.85 3 ICC CURRENT LIMIT (mA)
VCC vs VIN
ICC = 20mA TA = 25C 225 200 175 150 125 100 75
ICC Current Limit vs Temperature
0
5
10
15 20 25 ICC(LOAD) (mA)
30
35
40
4
5
6
7
8 VIN (V)
9
10
11
12
50 -50
-25
0 25 50 75 TEMPERATURE (C)
100
125
3845 G04
3845 G05
3845 G06
VCC UVLO Threshold (Rising) vs Temperature
6.5 VCC UVLO THRESHOLD, RISING (V) 25
ICC vs VCC (SHDN = 0V)
ERROR AMP TRANSCONDUCTANCE (S) TA = 25C 350 345 340 335 330 325
Error Amp Transconductance vs Temperature
6.4
20
6.2
ICC (A)
6.3
15
10
6.1
5
6.0 -50 -25
0 25 50 75 TEMPERATURE (C)
100
125
0
0
2
4
6
8
10 12 14 16 18 20 VCC (V)
3845 G08
320 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
3845 G07
3845 G09
I(SENSE+ + SENSE-) vs VSENSE(CM)
800 600 I(SENSE+ + SENSE-) (A) 400 200 0 -200 -400 TA = 25C OPERATING FREQUENCY (kHz) 308 306 304 302 300 298 296 294 292 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VSENSE(CM) (V)
3845 G10
Operating Frequency vs Temperature
1.234 1.233 ERROR AMP REFERENCE (V) 1.232 1.231 1.230 1.229 1.228
Error Amp Reference vs Temperature
290 -50
-25
0 25 50 75 TEMPERATURE (C)
100
125
1.227 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
3845 G11
3845 G12
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LT3845 TYPICAL PERFORMANCE CHARACTERISTICS
Maximum Current Sense Threshold vs Temperature
106 CURRENT SENSE THRESHOLD (mV) VIN UVLO THRESHOLD, RISING (V) 104 102 100 98 96 94 -50 -25 4.54 4.52 4.50 4.48 4.46 4.44 4.42 4.40 -50 -25
VIN UVLO Threshold (Rising) vs Temperature
3.86 VIN UVLO THRESHOLD, FALLING (V) 50 25 75 0 TEMPERATURE (C) 100 125
VIN UVLO Threshold (Falling) vs Temperature
3.84
3.82
3.80
3.78
50 25 75 0 TEMPERATURE (C)
100
125
3.76 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
3845 G13
3845 G14
3845 G15
TYPICAL APPLICATION
VIN (Pin 1): The VIN pin is the main supply pin and should be decoupled to SGND with a low ESR capacitor (at least 0.1F) located close to the pin. SHDN (Pin 2): The SHDN pin has a precision IC enable threshold of 1.35V (rising) with 120mV of hysteresis. It is used to implement an undervoltage lockout (UVLO) circuit. See Application Information section for implementing a UVLO function. When the SHDN pin is pulled below a transistor VBE (0.7V), a low current shutdown mode is entered, all internal circuitry is disabled and the VIN supply current is reduced to approximately 9A. Typical pin input bias current is <10nA and the pin is internally clamped to 6V. If the function is not used, this pin may be tied to VIN through a high value resistor. CSS (Pin 3): The soft-start pin is used to program the supply soft-start function. Use the following formula to calculate CSS for a given output voltage slew rate: CSS = 2A(tSS/1.231V) The pin should be left unconnected when not using the soft-start function. BURST_EN (Pin 4): Burst Mode Operation Enable Pin. This pin also controls reverse-current inhibit mode of operation. When the pin voltage is below 0.5V, Burst Mode operation and reverse-current inhibit functions are enabled. When the pin voltage is above 0.5V, Burst Mode operation is disabled, but reverse-current inhibit operation is maintained. In this mode of operation (BURST_EN = VFB) there is a 1mA minimum load requirement. Reverse-current inhibit is disabled when the pin voltage is above 2.5V. This pin is typically shorted to ground to enable Burst Mode operation and reverse-current inhibit, shorted to VFB to disable Burst Mode operation while enabling reverse-current inhibit, and connected to VCC pin to disable both functions. See Applications Information section. VFB (Pin 5): The output voltage feedback pin, VFB, is externally connected to the supply output voltage via a resistive divider. The VFB pin is internally connected to the inverting input of the error amplifier. In regulation, VFB is 1.231V. VC (Pin 6): The VC pin is the output of the error amplifier whose voltage corresponds to the maximum (peak) switch current per oscillator cycle. The error amplifier is typically configured as an integrator by connecting an RC network from the VC pin to SGND. This circuit creates the dominant pole for the converter regulation control loop. Specific integrator characteristics can be configured to optimize transient response. When Burst Mode operation is enabled (see Pin 4 description), an internal low impedance clamp on the VC pin is set at 100mV below the burst
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LT3845 PIN FUNCTIONS
threshold, which limits the negative excursion of the pin voltage. Therefore, this pin cannot be pulled low with a low impedance source. If the VC pin must be externally manipulated, do so through a 1k series resistance. SYNC (Pin 7): The Sync pin provides an external clock input for synchronization of the internal oscillator. RSET is set such that the internal oscillator frequency is 10% to 25% below the external clock frequency. If unused the Sync pin is connected to SGND. For more information see "Oscillator Sync" in the Application Information section of this datasheet. fSET (Pin 8): The fSET pin programs the oscillator frequency with an external resistor, RSET. The resistor is required even when supplying external sync clock signal. See the Applications Information section for resistor value selection details. SENSE- (Pin 9): The SENSE- pin is the negative input for the current sense amplifier and is connected to the VOUT side of the sense resistor for step-down applications. The sensed inductor current limit is set to 100mV across the SENSE inputs. SENSE+ (Pin 10): The SENSE+ pin is the positive input for the current sense amplifier and is connected to the inductor side of the sense resistor for step-down applications. The sensed inductor current limit is set to 100mV across the SENSE inputs. PGND (Pin 11): The PGND pin is the high-current ground reference for internal low side switch driver and the VCC regulator circuit. Connect the pin directly to the negative terminal of the VCC decoupling capacitor. See the Application Information section for helpful hints on PCB layout of grounds. BG (Pin 12): The BG pin is the gate drive for the bottom N-channel MOSFET. Since very fast high currents are driven from this pin, connect it to the gate of the power MOSFET with a short and wide, typically 0.02" width, PCB trace to minimize inductance. VCC (Pin 13): The VCC pin is the internal bias supply decoupling node. Use a low ESR, 1F or greater ceramic capacitor to decouple this node to PGND. Most internal IC functions are powered from this bias supply. An external diode connected from VCC to the BOOST pin charges the bootstrapped capacitor during the off-time of the main power switch. Back driving the VCC pin from an external DC voltage source, such as the VOUT output of the regulator supply, increases overall efficiency and reduces power dissipation in the IC. In shutdown mode this pin sinks 20A until the pin voltage is discharged to 0V. SW (Pin 14): Reference for VBOOST Supply and High Current Return for Bootstrapped Switch. TG (Pin 15): The TG pin is the bootstrapped gate drive for the top N-Channel MOSFET. Since very fast high currents are driven from this pin, connect it to the gate of the power MOSFET with a short and wide, typically 0.02" width, PCB trace to minimize inductance. BOOST (Pin 16): The BOOST pin is the supply for the bootstrapped gate drive and is externally connected to a low ESR ceramic boost capacitor referenced to SW pin. The recommended value of the BOOST capacitor,CBOOST, is at least 50 times greater than the total gate capacitance of the topside MOSFET. In most applications 0.1F is adequate. The maximum voltage that this pin sees is VIN + VCC, ground referred. SGND (Pin 17): The SGND pin is the low noise ground reference. It should be connected to the -VOUT side of the output capacitors. Careful layout of the PCB is necessary to keep high currents away from this SGND connection. See the Application Information section for helpful hints on PCB layout of grounds. Exposed Pad (SGND) (Pin 17): The exposed leadframe is internally connected to the SGND pin. Solder the exposed pad to the PCB ground for electrical contact and optimal thermal performance.
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LT3845
RB 11
4
5 ERROR AMP 100mV CURRENT SENSE COMPARATOR 0.5V
VFB OSCILLATOR
R1 gm Q S
- -
R SLOPE COMP GENERATOR
+
R2
RC
CC2 CC1
1V
VREF + 100mV
3 2A
CSS
CSS
-
+
FAULT CONDITIONS: VIN UVLO VCC UVLO VSHDN UVLO
+
CSS CLAMPED TO VREF + VBE Burst Mode OPERATION
-
-
6
VC
+
BURST_EN
+
+
-
-
+
+
-
8
BOOSTED SWITCH DRIVER BOOST 16 VCC UVLO (<6V) CBOOST 3.8V REG DRIVER DRIVE CONTROL 15 M1 TG INTERNAL SUPPLY RAIL BST UVLO 8V REG VREF SW 14 D1 13 CVCC DRIVER DRIVE CONTROL 12 PGND BG M2 L1 NOL SWITCH LOGIC VCC RSENSE VOUT COUT
VIN UVLO (<4V)
VIN
1
VIN
CIN
BLOCK DIAGRAM
RA
-
+
FEEDBACK REFERENCE 1.231V
2
SHDN
D2 (OPTIONAL)
SYNC fSET
7 8 RSET
Q
R
S
-
+
SOFT-START BURST DISABLE
REVERSE CURRENT INHIBIT
-
+
110mV
SGND
17
SENSE+ 10mV SENSE-
10 9
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LT3845 APPLICATIONS INFORMATION
Overview The LT3845 is a high input voltage range step-down synchronous DC/DC converter controller IC that uses a programmable constant frequency, current mode architecture with external N-channel MOSFET switches. The LT3845 has provisions for high efficiency, low load operation for battery-powered applications. Burst Mode operation reduces total average input quiescent currents to 120A during no load conditions. A low current shutdown mode can also be activated, reducing quiescent current to 10A. Burst Mode operation can be disabled if desired. A reverse-current inhibit feature allows increased efficiencies during light loads through nonsynchronous operation. This feature disables the synchronous switch if inductor current approaches zero. If full time synchronous operation is desired, this feature can be disabled. Much of the IC's internal circuitry is biased from an internal linear regulator. The output of this regulator is the VCC pin, allowing bypassing of the internal regulator. The associated internal circuitry can be powered from the output of the converter, increasing overall converter efficiency. Using externally derived power also eliminates the IC's power dissipation associated with the internal VIN to VCC regulator. Theory of Operation (See Block Diagram) The LT3845 senses converter output voltage via the VFB pin. The difference between the voltage on this pin and an internal 1.231V reference is amplified to generate an error voltage on the VC pin which is used as a threshold for the current sense comparator. During normal operation, the LT3845 internal oscillator runs at the programmed frequency. At the beginning of each oscillator cycle, the switch drive is enabled. The switch drive stays enabled until the sensed switch current exceeds the VC derived threshold for the current sense comparator and, in turn, disables the switch driver. If the current comparator threshold is not obtained for the entire oscillator cycle, the switch driver is disabled at the end of the cycle for 350ns, typical. This minimum off-time mode of operation assures regeneration of the BOOST bootstrapped supply. Power Requirements The LT3845 is biased using an internal linear regulator to generate operational voltages from the VIN pin. Virtually all of the circuitry in the LT3845 is biased via this internal linear regulator output (VCC). This pin is decoupled with a low ESR, 1F capacitor to PGND. The VCC regulator generates an 8V output provided there is ample voltage on the VIN pin. The VCC regulator has approximately 1V of dropout, and will follow the VIN pin with voltages below the dropout threshold. The LT3845 has a start-up requirement of VIN > 7.5V. This assures that the onboard regulator has ample headroom to bring the VCC pin above its UVLO threshold. The VCC regulator can only source current, so forcing the VCC pin above its 8V regulated voltage allows use of externally derived power for the IC, minimizing power dissipation in the IC. Using the onboard regulator for start-up, then deriving power for VCC from the converter output maximizes conversion efficiencies and is common practice. If VCC is maintained above 6.5V using an external source, the LT3845 can continue to operate with VIN as low as 4V. The LT3845 operates with 3mA quiescent current from the VCC supply. This current is a fraction of the actual VCC quiescent currents during normal operation. Additional current is produced from the MOSFET switching currents for both the boosted and synchronous switches and are typically derived from the VCC supply. Because the LT3845 uses a linear regulator to generate VCC, power dissipation can become a concern with high VIN voltages. Gate drive currents are typically in the range of 5mA to 15mA per MOSFET, so gate drive currents can create substantial power dissipation. It is advisable to derive VCC and VBOOST power from an external source whenever possible. The onboard VCC regulator will provide gate drive power for start-up under all conditions with total MOSFET gate charge loads up to 180nC. The regulator can operate the LT3845 continuously, provided the power dissipation of the regulator does not exceed 250mW. The power dissipaton of the regulator is calculated as follows: PD(REG) = (VIN - 8V) * (fSW * QG(TOTAL) + 3mA)
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LT3845 APPLICATIONS INFORMATION
where QG(TOTAL) is the total MOSFET gate charge of the TG and BG. In applications where these conditions are exceeded, VCC must be derived from an external source after start-up. Maximum continuous regulator power dissipation may be exceeded for short duration VIN transients. In LT3845 converter applications with output voltages in the 9V to 20V range, back-feeding VCC and VBOOST from the converter output is trivial, accomplished by connecting diodes from the output to these supply pins. Deriving these supplies from output voltages greater than 20V will require additional regulation to reduce the feedback voltage. Outputs lower than 9V will require step-up techniques to increase the feedback voltage to something greater than the 8V VCC regulated output. Low power boost switchers are sometimes used to provide the step-up function, but a simple charge-pump can perform this function in many instances.
Charge Pump Doubler
VOUT B0520 VCC 1F LT3845 Si1555DL 1F B0520
Inductor Auxiliary Winding
TG SW LT3845 VCC
*
N
VOUT
*
BG
3845 AI04
Burst Mode The LT3845 employs low current Burst Mode functionality to maximize efficiency during no load and low load conditions. Burst Mode operation is enabled by shorting the BURST_EN pin to SGND. Burst Mode operation can be disabled by shorting BURST_EN to either VFB or VCC. When the required switch current, sensed via the VC pin voltage, is below 15% of maximum, the Burst Mode operation is employed and that level of sense current is latched onto the IC control path. If the output load requires less than this latched current level, the converter will overdrive the output slightly during each switch cycle. This overdrive condition is sensed internally and forces the voltage on the VC pin to continue to drop. When the voltage on VC drops 150mV below the 15% load level, switching is disabled and the LT3845 shuts down most of its internal circuitry, reducing total quiescent current to 120A. When the converter output begins to fall, the VC pin voltage begins to climb. When the voltage on the VC pin climbs back to the 15% load level, the IC returns to normal operation and switching resumes. An internal clamp on the VC pin is set at 100mV below the switch disable threshold, which limits the negative excursion of the pin voltage, minimizing the converter output ripple during Burst Mode operation. During Burst Mode operation, VIN pin current is 20A and VCC current is reduced to 100A. If no external drive is provided for VCC, all VCC bias currents originate from the
BG
Charge Pump Tripler
VOUT B0520 B0520 1F
B0520 VCC 1F LT3845
1F
Si1555DL
Si1555DL
3845 AI01
BG
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LT3845 APPLICATIONS INFORMATION
VIN pin, giving a total VIN current of 120A. Burst current can be reduced further when VCC is driven using an output derived source, as the VCC component of VIN current is then reduced by the converter buck ratio. Reverse-Current Inhibit The LT3845 contains a reverse-current inhibit feature to maximize efficiency during light load conditions. This mode of operation allows discontinuous operation and pulse-skipping mode at light loads. Refer to Figure 1. This feature is enabled with Burst Mode operation, and can also be enabled while Burst Mode operation is disabled by shorting the BURST_EN pin to VFB. When reverse-current inhibit is enabled, the LT3845 sense amplifier detects inductor currents approaching zero and disables the synchronous switch for the remainder of the switch cycle. If the inductor current is allowed to go negative before the synchronous switch is disabled, the switch node could inductively kick positive with a high dv/dt. The LT3845 prevents this by incorporating a 10mV positive offset at the sense inputs. With the reverse-current inhibit feature enabled, an LT3845 converter will operate much like a nonsynchronous converter during light loads. Reverse-current inhibit reduces resistive losses associated with inductor ripple currents, which improves operating efficiencies during light-load conditions. An LT3845 DC/DC converter that is operating in reversecurrent inhibit mode has a minimum load requirement of 1mA (BURST_EN = VFB). Since most applications use output-generated power for the LT3845, this requirement is met by the bias currents of the IC, however, for applications that do not derive power from the output, this requirement is easily accomplished by using a 1.2k resistor connected from VFB to ground as one of the converter output voltage programming resistors (R1). There are no minimum load restrictions when in Burst Mode operation (BURST_EN < 0.5V) or continuous conduction mode (BURST_EN > 2.5V). Soft-Start The soft-start function controls the slew rate of the power supply output voltage during start-up. A controlled output voltage ramp minimizes output voltage overshoot, reduces inrush current from the VIN supply, and facilitates supply sequencing. A capacitor, CSS, connected from the CSS pin to SGND, programs the slew rate. The capacitor is charged from an internal 2A current source producing a ramped voltage. The capacitor voltage overrides the internal reference to the error amplifier. If the VFB pin voltage exceeds the CSS pin voltage then the current threshold set by the DC control voltage, VC, is decreased and the inductor current is lowered. This in turn decreases the output voltage slew rate allowing the CSS pin voltage ramp to catch up to the VFB pin voltage. An internal 100mV offset is added to the VFB pin voltage relative to the CSS pin voltage so that
IL
PULSE SKIP MODE
IL
FORCED CONTINUOUS
DECREASING LOAD CURRENT
3845 F01
Figure 1. Inductor Current vs Mode
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LT3845 APPLICATIONS INFORMATION
at start-up the soft-start circuit will discharge the VC pin voltage below the DC control voltage equivalent to zero inductor current. This will reduce the input supply inrush current. The soft-start circuit is disabled once the CSS pin voltage has been charged to 200mV above the internal reference of 1.231V. During a VIN UVLO, VCC UVLO or SHDN UVLO event, the CSS pin voltage is discharged with a 50A current source. In normal operation the CSS pin voltage is clamped to a diode above the VFB pin voltage. Therefore, the value of the CSS capacitor is relevant to how long of a fault event will retrigger a soft-start. If any of the above UVLO conditions occur, the CSS pin voltage will be discharged with a 50A current source. There is a diode worth of voltage headroom to ride through the fault before the CSS pin voltage enters its active region and the soft-start function is enabled. Also, since the CSS pin voltage is clamped to a diode above the VFB pin voltage, during a short circuit the CSS pin voltage is pulled low because the VFB pin voltage is low. Once the short has been removed the VFB pin voltage starts to recover. The soft-start circuit takes control of the output voltage slew rate once the VFB pin voltage has exceeded the slowly ramping CSS pin voltage, reducing the output voltage overshoot during a short circuit recovery. Adaptive Nonoverlap (NOL) Output Stage The FET driver output stages implement adaptive nonoverlap control. This feature maintains a constant dead time, preventing shoot-through switch currents, independent of the type, size or operating conditions of the external switch elements. Each of the two switch drivers contains a NOL control circuit, which monitors the output gate drive signal of the other switch driver. The NOL control circuits interrupt the "turn on" command to their associated switch driver until the other switch gate is fully discharged. Antislope Compensation Most current mode switching controllers use slope compensation to prevent current mode instability. The LT3845 is no exception. A slope-compensation circuit imposes an artificial ramp on the sensed current to increase the rising slope as duty cycle increases. Unfortunately, this additional ramp corrupts the sensed current value, reducing the achievable current limit value by the same amount as the added ramp represents. As such, current limit is typically reduced as duty cycles increase. The LT3845 contains circuitry to eliminate the current limit reduction typically associated with slope compensation. As the slope-compensation ramp is added to the sensed current, a similar ramp is added to the current limit threshold reference. The end result is that current limit is not compromised, so an LT3845 converter can provide full power regardless of required duty cycle. Shutdown The LT3845 SHDN pin uses a bandgap generated reference threshold of 1.35V. This precision threshold allows use of the SHDN pin for both logic-level controlled applications and analog monitoring applications such as power supply sequencing. The LT3845 operational status is primarily controlled by a UVLO circuit on the VCC regulator pin. When the IC is enabled via the SHDN pin, only the VCC regulator is enabled. Switching remains disabled until the UVLO threshold is achieved at the VCC pin, when the remainder of the IC is enabled and switching commences. Because an LT3845 controlled converter is a power transfer device, a voltage that is lower than expected on the input supply could require currents that exceed the sourcing capabilities of that supply, causing the system to lock up in an undervoltage state. Input supply start-up protection can be achieved by enabling the SHDN pin using a resistive divider from the VIN supply to ground. Setting the divider output to 1.35V when that supply is at an adequate voltage prevents an LT3845 converter from drawing large currents until the input supply is able to provide the required power. 120mV of input hysteresis on the SHDN pin allows for almost 10% of input supply droop before disabling the converter. RSENSE Selection The current sense resistor, RSENSE, monitors the inductor current of the supply (See Typical Application on front page). Its value is chosen based on the maximum required output load current. The LT3845 current sense amplifier
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12
LT3845 APPLICATIONS INFORMATION
has a maximum voltage threshold of, typically, 100mV. Therefore, the peak inductor current is 100mV/RSENSE. The maximum output load current, IOUT(MAX), is the peak inductor current minus half the peak-to-peak ripple current, IL. Allowing adequate margin for ripple current and external component tolerances, RSENSE can be calculated as follows: RSENSE = 70mV IOUT(MAX) architecture that can be programmed over a 100kHz to 500kHz range with a single resistor from the fSET pin to ground, as shown in Figure 2. The nominal voltage on the fSET pin is 1V and the current that flows from this pin is used to charge an internal oscillator capacitor. The value of RSET for a given operating frequency can be chosen from Figure 2 or from the following equation: RSET(k) = 8.4 * 104 * fSW(-1.31) Table 1 lists typical resistor values for common operating frequencies.
Table 1. Recommended 1% Standard Values
RSET 191k 118k 80.6k 63.4k 49.9k 40.2k 33.2k 27.4k 23.2k fSW 100kHz 150kHz 200kHz 250kHz 300kHz 350kHz 400kHz 450kHz 500kHz
Typical values for RSENSE are in the range of 0.005 to 0.05. Operating Frequency The choice of operating frequency is a trade off between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching losses and gate charge losses. However, lower frequency operation requires more inductance for a given amount of ripple current, resulting in a larger inductor size and higher cost. If the ripple current is allowed to increase, larger output capacitors may be required to maintain the same output ripple. For converters with high step-down VIN to VOUT ratios, another consideration is the minimum on-time of the LT3845 (see the Minimum On-time Considerations section). A final consideration for operating frequency is that in noise-sensitive communications systems, it is often desirable to keep the switching noise out of a sensitive frequency band. The LT3845 uses a constant frequency
200 180 160 140 RSET (k) 120 100 80 60 40 20 0 100 300 200 400 FREQUENCY (kHz) 500 600
3845 F2
Inductor Selection The critical parameters for selection of an inductor are minimum inductance value, volt-second product, saturation current and/or RMS current. For a given IL, The minimum inductance value is calculated as follows: L VOUT * VIN(MAX) - VOUT fSW * VIN(MAX) * IL
fSW is the switch frequency. The typical range of values for IL is (0.2 * IOUT(MAX)) to (0.5 * IOUT(MAX)), where IOUT(MAX) is the maximum load current of the supply. Using IL = 0.3 * IOUT(MAX) yields a good design compromise between inductor performance versus inductor size and cost. A value of IL = 0.3 * IOUT(MAX) produces a 15% of IOUT(MAX) ripple current around the DC output current of the supply. Lower values of IL require larger and more costly magnetics. Higher values of IL
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Figure 2. Timing Resistor (RSET) Value
13
LT3845 APPLICATIONS INFORMATION
will increase the peak currents, requiring more filtering on the input and output of the supply. If IL is too high, the slope compensation circuit is ineffective and current mode instability may occur at duty cycles greater than 50%. To satisfy slope compensation requirements the minimum inductance is calculated as follows: LMIN > VOUT * 2DCMAX - 1 RSENSE * 8.33 * DCMAX fSW balancing the transition losses with the conduction losses is a good idea while the bottom MOSFET is dominated by the conduction loss, which is worse during a short-circit condition or at a very low duty cycle. Calculate the maximum conduction losses of the MOSFETs: V PCOND(TOP) = IOUT(MAX)2 * OUT * RDS(ON) VIN PCOND(BOT) = IOUT(MAX)2 * VIN - VOUT * RDS(ON) VIN
The magnetics vendors specify either the saturation current, the RMS current or both. When selecting an inductor based on inductor saturation current, use the peak current through the inductor, IOUT(MAX) + IL/2. The inductor saturation current specification is the current at which the inductance, measured at zero current, decreases by a specified amount, typically 30%. When selecting an inductor based on RMS current rating, use the average current through the inductor, IOUT(MAX). The RMS current specification is the RMS current at which the part has a specific temperature rise, typically 40C, above 25C ambient. After calculating the minimum inductance value, the volt-second product, the saturation current and the RMS current for your design, select an off-the-shelf inductor. Contact the Application group at Linear Technology for further support. For more detailed information on selecting an inductor, please see the "Inductor Selection" section of Linear Technology Application Note 44. MOSFET Selection The selection criteria of the external N-channel standard level power MOSFETs include on resistance (RDS(ON)), reverse transfer capacitance (CRSS), maximum drain source voltage (VDSS), total gate charge (QG) and maximum continuous drain current. For maximum efficiency, minimize RDS(ON) and CRSS. Low RDS(ON) minimizes conduction losses while low CRSS minimizes transition losses. The problem is that RDS(ON) is inversely related to CRSS. In selecting the top MOSFET
Note that RDS(ON) has a large positive temperature dependence. The MOSFET manufacturer's data sheet contains a curve, RDS(ON) vs Temperature. In the main MOSFET, transition losses are proportional to VIN2 and can be considerably large in high voltage applications (VIN > 20V). Calculate the maximum transition losses: PTRAN(TOP) = k * VIN2 * IOUT(MAX) * CRSS * fSW where k is a constant inversely related to the gate driver current, approximated by k = 2 for LT3845 applications. The total maximum power dissipations of the MOSFET are: PTOP(TOTAL) = PCOND(MAIN) + PTRAN(MAIN) PBOT(TOTAL) = PCOND(SYNC) To achieve high supply efficiency, keep the total power dissipation in each switch to less than 3% of the total output power. Also, complete a thermal analysis to ensure that the MOSFET junction temperature is not exceeded. TJ = TA + P(TOTAL) * JA where JA is the package thermal resistance and TA is the ambient temperature. Keep the calculated TJ below the maximum specified junction temperature, typically 150C. Note that when VIN is high and fSW is high, the transition losses may dominate. A MOSFET with higher RDS(ON) and lower CRSS may provide higher efficiency. MOSFETs with higher voltage VDSS specification usually have higher RDS(ON) and lower CRSS.
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14
LT3845 APPLICATIONS INFORMATION
Choose the MOSFET VDSS specification to exceed the maximum voltage across the drain to the source of the MOSFET, which is VIN(MAX) plus any additional ringing on the switch node. Ringing on the switch node can be greatly reduced with good PCB layout and, if necessary, an RC snubber. In some applications, parasitic FET capacitances couple the negative going switch node transient onto the bottom gate drive pin of the LT3845, causing a negative voltage in excess of the Absolute Maximum Rating to be imposed on that pin. Connection of a catch Schottky diode from this pin to ground will eliminate this effect. A 1A current rating is typically sufficient of the diode. The internal VCC regulator is capable of sourcing up to 40mA limiting the maximum total MOSFET gate charge, QG, to 35mA/fSW. The QG vs VGS specification is typically provided in the MOSFET data sheet. Use QG at VGS of 8V. If VCC is back driven from an external supply, the MOSFET drive current is not sourced from the internal regulator of the LT3845 and the QG of the MOSFET is not limited by the IC. However, note that the MOSFET drive current is supplied by the internal regulator when the external supply back driving VCC is not available such as during start-up or short circuit. The manufacturer's maximum continuous drain current specification should exceed the peak switch current, IOUT(MAX) + IL/2. During the supply start-up, the gate drive levels are set by the VCC voltage regulator, which is approximately 8V. Once the supply is up and running, the VCC can be back driven by an auxiliary supply such as VOUT. It is important not to exceed the manufacturer's maximum VGS specification. A standard level threshold MOSFET typically has a VGS maximum of 20V. Input Capacitor Selection A local input bypass capacitor is required for buck converters because the input current is pulsed with fast rise and fall times. The input capacitor selection criteria are based on the bulk capacitance and RMS current capability. The bulk capacitance will determine the supply input ripple voltage. The RMS current capability is used to prevent overheating the capacitor. The bulk capacitance is calculated based on maximum input ripple, VIN: CIN(BULK) = IOUT(MAX) * VOUT VIN * fSW * VIN(MIN)
VIN is typically chosen at a level acceptable to the user. 100mV to 200mV is a good starting point. Aluminum electrolytic capacitors are a good choice for high voltage, bulk capacitance due to their high capacitance per unit area. The capacitor's RMS current is: ICIN(RMS) =IOUT VOUT (VIN - VOUT ) (VIN )2
If applicable, calculate it at the worst case condition, VIN = 2VOUT. The RMS current rating of the capacitor is specified by the manufacturer and should exceed the calculated ICIN(RMS). Due to their low ESR (Equivalent Series Resistance), ceramic capacitors are a good choice for high voltage, high RMS current handling. Note that the ripple current ratings from aluminum electrolytic capacitor manufacturers are based on 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. The combination of aluminum electrolytic capacitors and ceramic capacitors is an economical approach to meeting the input capacitor requirements. The capacitor voltage rating must be rated greater than VIN(MAX). Multiple capacitors may also be paralleled to meet size or height requirements in the design. Locate the capacitor very close to the MOSFET switch and use short, wide PCB traces to minimize parasitic inductance. Output Capacitor Selection The output capacitance, COUT, selection is based on the design's output voltage ripple, VOUT and transient load requirements. VOUT is a function of IL and the COUT ESR. It is calculated by: 1 VOUT = IL * ESR + (8 * fSW * COUT )
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15
LT3845 APPLICATIONS INFORMATION
The maximum ESR required to meet a VOUT design requirement can be calculated by: ESR(MAX) = (VOUT )(L)(fSW ) V VOUT * 1- OUT VIN(MAX) The VFB pin input bias current is typically 25nA, so use of extremely high value feedback resistors could cause a converter output that is slightly higher than expected. Bias current error at the output can be estimated as: VOUT(BIAS) = 25nA * R2 Supply UVLO and Shutdown The SHDN pin has a precision voltage threshold with hysteresis which can be used as an undervoltage lockout threshold (UVLO) for the power supply. Undervoltage lockout keeps the LT3845 in shutdown until the supply input voltage is above a certain voltage programmed by the user. The hysteresis voltage prevents noise from falsely tripping UVLO. Resistors are chosen by first selecting RB. Then VSUPPLY(ON) RA = RB * - 1 1.35V VSUPPLY(ON) is the input voltage at which the undervoltage lockout is disabled and the supply turns on. Example: Select RB = 49.9k, VSUPPLY(ON) = 14.5V (based on a 15V minimum input voltage) 14.5V RA = 49.9k * -1 1.35V = 486.1k (499k resistor is selected)
Worst-case VOUT occurs at highest input voltage. Use paralleled multiple capacitors to meet the ESR requirements. Increasing the inductance is an option to lower the ESR requirements. For extremely low VOUT, an additional LC filter stage can be added to the output of the supply. Application Note 44 has some good tips on sizing an additional output filter. Output Voltage Programming A resistive divider sets the DC output voltage according to the following formula: V R2 = R1 OUT - 1 1.231V The external resistor divider is connected to the output of the converter as shown in Figure 3. Tolerance of the feedback resistors will add additional error to the output voltage. Example: VOUT = 12V; R1 = 10k 12V R2 = 10k - 1 = 87.48k - use 86.6k 1% 1.231V
L1 VOUT R2 VFB PIN R1
3845 F03
VSUPPLY RA SHDN PIN RB
3845 F04
COUT
Figure 3. Output Voltage Feedback Divider
Figure 4. Undervoltage Feedback Divider
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16
LT3845 APPLICATIONS INFORMATION
If low supply current in standby mode is required, select a higher value of RB. The supply turn off voltage is 9% below turn on. In the example the VSUPPLY(OFF) would be 13.2V. If additional hysteresis is desired for the enable function, an external positive feedback resistor can be used from the LT3845 regulator output. The shutdown function can be disabled by connecting the SHDN pin to the VIN through a large value pull-up resistor. This pin contains a low impedance clamp at 6V, so the SHDN pin will sink current from the pull-up resistor(RPU): ISHDN = VIN - 6V RPU It is recommended that the SYNC pin be driven with a square wave that has amplitude greater than 2V, pulse width greater than 1s and rise time less than 500ns. The rising edge of the sync wave form triggers the discharge of the internal oscillator capacitor. Minimum On-Time Considerations (Buck Mode) Minimum on-time tON(MIN) is the smallest amount of time that the LT3845 is capable of turning the top MOSFET on and off again. It is determined by internal timing delays and the amount of gate charge required turning on the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: tON = VOUT > tON(MIN) VIN * fSW
Because this arrangement will clamp the SHDN pin to the 6V, it will violate the 5V absolute maximum voltage rating of the pin. This is permitted, however, as long as the absolute maximum input current rating of 1mA is not exceeded. Input SHDN pin currents of <100A are recommended: a 1M or greater pull-up resistor is typically used for this configuration. Soft-Start The desired soft-start time (tSS) is programmed via the CSS capacitor as follows: CSS 2A * tSS = 1.231V
where tON(MIN) is 400ns worst case. If the duty cycle falls below what can be accommodated by the minimum on-time, the LT3845 will begin to skip cycles. The output will be regulated, but the ripple current and ripple voltage will increase. If lower frequency operation is acceptable, the on-time can be increased above tON(MIN) for the same step-down ratio. Layout Considerations The LT3845 is typically used in DC/DC converter designs that involve substantial switching transients. The switch drivers on the IC are designed to drive large capacitances and, as such, generate significant transient currents themselves. Careful consideration must be made regarding supply bypass capacitor locations to avoid corrupting the ground reference used by IC. Typically, high current paths and transients from the input supply and any local drive supplies must be kept isolated from SGND, to which sensitive circuits such as the error amp reference and the current sense circuits are referred. Effective grounding can be achieved by considering switch current in the ground plane, and the return current paths of each respective bypass capacitor. The VIN bypass return, VCC bypass return, and the source of the synchronous
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The amount of time in which the power supply can withstand a VIN, VCC or VSHDN UVLO fault condition (tFAULT) before the CSS pin voltage enters its active region is approximated by the following formula: tFAULT C * 0.65V = SS 50A
Oscillator SYNC The oscillator can be synchronized to an external clock. Set the RSET resistor at least 10% below the desired sync frequency.
17
LT3845 APPLICATIONS INFORMATION
FET carry PGND currents. SGND originates at the negative terminal of the VOUT bypass capacitor, and is the small signal reference for the LT3845. Don't be tempted to run small traces to separate ground paths. A good ground plane is important as always, but PGND referred bypass elements must be oriented such that transient currents in these return paths do not corrupt the SGND reference. During the dead-time between switch conduction, the body diode of the synchronous FET conducts inductor current. Commutating this diode requires a significant charge contribution from the main switch. At the instant the body diode commutates, a current discontinuity is created and parasitic inductance causes the switch node to fly up in response to this discontinuity. High currents and excessive parasitic inductance can generate extremely fast dV/dt rise times. This phenomenon can cause avalanche breakdown in the synchronous FET body diode, significant inductive overshoot on the switch node, and shoot-through currents via parasitic turn-on of the synchronous FET. Layout practices and component orientations that minimize parasitic inductance on this node is critical for reducing these effects. Ringing waveforms in a converter circuit can lead to device failure, excessive EMI, or instability. In many cases, you can damp a ringing waveform with a series RC network across the offending device. In LT3845 applications, any ringing will typically occur on the switch node, which can usually be reduced by placing a snubber across the synchronous FET. Use of a snubber network, however, should be considered a last resort. Effective layout practices typically reduce ringing and overshoot, and will eliminate the need for such solutions. Effective grounding techniques are critical for successful DC/DC converter layouts. Orient power path components such that current paths in the ground plane do not cross through signal ground areas. Signal ground refers to the Exposed Pad on the backside of the LT3845 IC. SGND is referenced to the (-) terminal of the VOUT decoupling capacitor and is used as the converter voltage feedback reference. Power ground currents are controlled on the LT3845 via the PGND pin, and this ground references the high current synchronous switch drive components, as well as the local VCC supply. It is important to keep PGND and SGND voltages consistent with each other, so separating these grounds with thin traces is not recommended. When the synchronous FET is turned on, gate drive surge currents return to the LT3845 PGND pin from the FET source. The BOOST supply refresh surge currents also return through this same path. The synchronous FET must be oriented such that these PGND return currents do not corrupt the SGND reference. Problems caused by the PGND return path are generally recognized during heavy load conditions, and are typically evidenced as multiple switch pulses occurring during a single switch cycle. This behavior indicates that SGND is being corrupted and grounding should be improved. SGND corruption can often be eliminated, however, by adding a small capacitor (100pF to 200pF) across the synchronous switch FET from drain to source. The high di/dt loop formed by the switch MOSFETs and the input capacitor (CIN) should have short wide traces to minimize high frequency noise and voltage stress from inductive ringing. Surface mount components are preferred to reduce parasitic inductances from component leads. Connect the drain of the main switch MOSFET directly to the (+) plate of CIN, and connect the source of the synchronous switch MOSFET directly to the (-) terminal of CIN. This capacitor provides the AC current to the switch MOSFETs. Switch path currents can be controlled by orienting switch FETs, the switched inductor, and input and output decoupling capacitors in close proximity to each other. Locate the VCC and BOOST decoupling capacitors in close proximity to the IC. These capacitors carry the MOSFET drivers' high peak currents. Locate the small-signal components away from high frequency switching nodes (BOOST, SW, TG, VCC and BG). Small-signal nodes are oriented on the left side of the LT3845, while high current switching nodes are oriented on the right side of the IC to simplify layout. This also helps prevent corruption of the SGND reference. Connect the VFB pin directly to the feedback resistors independent of any other nodes, such as the SENSE- pin. The feedback resistors should be connected between the (+) and (-) terminals of the output capacitor (COUT).
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18
LT3845 APPLICATIONS INFORMATION
Locate the feedback resistors in close proximity to the LT3845 to minimize the length of the high impedance VFB node. The SENSE- and SENSE+ traces should be routed together and kept as short as possible. The LT3845 packaging has been designed to efficiently remove heat from the IC via the Exposed Pad on the backside of the package. The Exposed Pad is soldered to a copper footprint on the PCB. This footprint should be made as large as possible to reduce the thermal resistance of the IC case to ambient air.
Orientation of Components Isolates Power Path and PGND Currents, Preventing Corruption of SGND Reference
VIN BOOST SW SGND REFERRED COMPONENTS LT3845 VCC SGND PGND
+
TG SW
BG
3845 AI03
VOUT
+
ISENSE
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19
LT3845 TYPICAL APPLICATIONS
9V-16V to 3.3V at 10A DC/DC Converter Capable of Withstanding 60V Transients, All Ceramic Capacitors and Soft-Start Enabled
VIN 9V TO 16V 60V TRANSIENTS
CIN 2.2F 100V x4
CIN2 0.1F 100V
R3 1.1M
C5 1F 16V 1 2 3 VIN SHDN CSS LT3845 BOOST TG SW VCC BG PGND SENSE+ SENSE- SGND 17 16 15 14 13 12 11 10 9 C4 2.2F 16V D2A BAV99 M2 Si7370DP COUT 100F 6.3V x5 M1 Si7370DP D1 L1 3.3H RSENSE 0.006
C3 8200pF
4 5 6
VOUT 3.3V 10A
BURST_EN VFB VC SYNC fSET
R1 10k R2 16.9k
SYNC R4 25k R5 100k
7 8
C2 R6 6800pF 49.9k
CIN: TDK C4532X7R2A225K COUT: MURATA GRM32ER60J107ME20 D1: DIODES INC. B3100 L1: WURTH 7443551370
VIN R7 4.99k D3 12V Q1 60V D2B BAV99
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Efficiency and Power Loss
95 90 BATTERY VOLTAGE (V) VIN = 9V POWER LOSS (W) 85 80 75 70 65 0.1 4 3 VIN = 16V 2 1 0 10
3845 TA02b
6 5
VIN = 14V
POWER LOSS VIN = 14V 1 LOAD CURRENT (A)
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LT3845 TYPICAL APPLICATIONS
9V-16V to 5V at 10A DC/DC Converter, 500kHz Frequency Operation, Capable of Withstanding 36V Transients, All Ceramic Capacitors, Soft-Start and Burst Mode Enabled
VIN 9V TO 16V 36V TRANSIENTS
CIN 6.8F 50V x4
CIN2 0.1F 50V C3 8200pF
R3 1.1M
C5 1F 16V 1 2 3 4 5 6 VIN SHDN CSS LT3845 BOOST TG SW VCC BG PGND SENSE
+
16 15 14 13 12 11 10 9 C4 2.2F 16V D2 BAS19 M2 Si7884DP COUT 100F 6.3V x4 M1 Si7884DP D1 L1 2.7H RSENSE 0.005
VOUT 5V 10A
BURST_EN VFB VC SYNC fSET SGND 17
R1 49.9k R2 154k C1 100pF R4 10k C2 R6 5600pF 23.2k
7 8
SENSE-
CIN: TDK C4532X7R1H685K COUT: MURATA GRM32ER60J107ME20 D1: DIODES INC. B170 L1: WURTH 744318270LF
D3B BAV99 D3A BAV99 C6 1F Si1555DL
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Efficiency and Power Loss
100 95 EFFICIENCY (%) 90 85 80 75 70 0.1 POWER LOSS VIN = 14V 1 LOAD CURRENT (A) VIN = 9V 6 5 POWER LOSS (W) 4 3 2 1 0 10
3845 TA03b
VIN = 14V VIN = 16V
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LT3845 TYPICAL APPLICATIONS
9V-24V to 3.3V, 2-Phase at 10A per Phase, DC/DC Converter with Spread Spectrum Operation
VIN 24V
CIN 6.8F 50V x2
R3 1.21M
C5 1F 16V 1 2 VIN SHDN CSS LT3845 BOOST TG SW VCC BG PGND SENSE+ SENSE- SGND 17 16 15 14 13 12 11 10 9 C4 2.2F 16V D2 BAS19 M2 Si7850DP M1 Si7850DP L1 4.7H D1 B160 RSENSE 0.005
R4 1.21M
C3 8200pF 3 4 5 6 C11 SYNC 47pF R6 130k 7 8
BURST_EN VFB VC SYNC fSET
R12 25k Q1 D5 5.7V CIN3 0.1F 100V 1 C11 0.1F 1 R11 500k 2 V OUT1 LTC6908-1 5 SYNC2 GND OUT2 3 4 SET3 MOD
+
VOUT 3.3V 20A C10 1F 16V VIN SHDN CSS LT3845 BOOST TG SW VCC BG PGND SENSE+ SENSE- SGND 17 16 15 14 13 12 11 10 9 C9 2.2F 16V D4 BAS19 M4 Si7850DP M3 Si7850DP L2 4.7H D3 B160 2 C8 8200pF 3 4 5 6 R1 10k R2 16.8k C6 47pF
COUT 100F 6.3V x6
6
SYNC1
RSENSE2 0.005
BURST_EN VFB VC
7 SYNC SYNC R9 8 4.99k fSET C7 R10 5600pF 130k
CIN: TDK C4532X7R1H685K COUT: MURATA GRM32ER60J107ME20 D1, D3: DIODES, INC. B160 L1, L2: VISHAY IHLP-5050FD-01
3845 TA05
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22
LT3845 PACKAGE DESCRIPTION
FE Package 16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BC
4.90 - 5.10* (.193 - .201) 3.58 (.141) 16 1514 13 12 1110 9
3.58 (.141)
6.60 0.10 4.50 0.10
SEE NOTE 4
2.94 (.116) 0.45 0.05 1.05 0.10 0.65 BSC
6.40 2.94 (.252) (.116) BSC
RECOMMENDED SOLDER PAD LAYOUT
12345678 1.10 (.0433) MAX
0 - 8
4.30 - 4.50* (.169 - .177)
0.25 REF
0.09 - 0.20 (.0035 - .0079)
0.50 - 0.75 (.020 - .030)
0.65 (.0256) BSC
NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE
0.195 - 0.30 (.0077 - .0118) TYP
0.05 - 0.15 (.002 - .006)
FE16 (BC) TSSOP 0204
4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LT3845 TYPICAL APPLICATION
9V-16V to 3.3V at 5A DC/DC Converter, Frequency Synchronization Range 150kHz to 300kHz, Capable of Withstanding 60V Transients, All Ceramic Capacitors, Soft-Start and Burst Mode Enabled
VIN 9V TO 16V 60V TRANSIENTS
CIN 2.2F 100V x4
CIN2 0.1F 100V C3 8200pF
R3 1.1M
C5 1F 16V 1 2 3 4 5 6 VIN SHDN CSS LT3845 BOOST TG SW VCC BG PGND SENSE+ SENSE- SGND 17 16 15 14 13 12 11 10 9 C4 2.2F 16V D2 BAS521 M2 Si7850DP COUT 100F 6.3V x4 M1 Si7850DP L1 10H D1 B160 RSENSE 0.01
VOUT 3.3V 5A
BURST_EN VFB VC SYNC fSET
R1 10k C1 R2 16.8k 100pF
SYNC R4 10k C2 5600pF R5 100k R6 130k
7 8
3845 TA04
CIN: TDK C4532X7R2A225K COUT: MURATA GRM32ER60J107ME20 L1: VISHAY IHLP-5050FD-01 M1, M2: VISHAY Si7850DP
RELATED PARTS
PART NUMBER LT1339 LTC 1624 LTC1702A LTC1735 LTC1778 LT3010 LT3430/LT3431 LTC3703/LTC3703-5 LT3724 LT3800 LT3844
(R)
DESCRIPTION High Power Synchronous DC/DC Controller Switching Controller Dual 2-Phase Synchronous DC/DC Controller Synchronous Step-Down DC/DC Controller No RSENSETM Synchronous DC/DC Controller 50mA, 3V to 80V Linear Regulator Monolithic 3A, 200kHz/500kHz Step-Down Regulator 100V Synchronous Switching Regulator Controllers High Voltage Current Mode Switching Regulator Controllers High Voltage Synchronous Regulator Controller High Voltage Current Mode Controller with Programmable Operating Frequency
COMMENTS VIN up to 60V, Drivers 10000pF Gate Capacitance, IOUT = <20A Buck, Boost, SEPIC, 3.5V VIN 36V; 8-Lead SO Package 550kHz Operation, No RSENSE, 3V = No RSENSE is a trademark of Linear Technology Corporation.
3845fc
24 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 0707 REV C * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2006

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